DIGITAL DESIGN VERIFICATION

Experience

The complexity of current verification projects requires large teams of designers, test and verification engineers to collaborate seamlessly across a development flow of many stages.

Verification work is placed in the middle of the process, at the confluence of data, constraints and changes. The verification code is subject to review, use and extensions by all participants. It also tends to represent a significantly larger investment of effort and resources than the RTL design itself.

Observing these forces, NoBug has always aimed towards a componentized approach to the development of verification environments and test benches, and based it on sound methodology.

NoBug has been an early adopter of methodologies promoting reuse, interoperability and seamless integration of verification components.

Methodology

We are able to deliver a predictable verification process because our work is based on an effective and comprehensive methodology. Our verification methodology is consistent with industry standard methodology proposals such as eRM, RVM, VMM, sVM, AVM, OVM and uVM.

We are actively developing it to ensure a standard, uniform approach from one project to the next, although this is especially a challenge with their quickly changing scope and nature.

We extensively rely upon the use of templates and guidelines for the specification and code items. In some cases, this process is supported by custom software tools that generate automatically the skeleton infrastructure for parts of a project.

An important role in assuring the consistency and quality of the planning, documenting and testing phases is played by the peer reviews of these items. These reviews are planned into the workflow and their outcome is observed in the development.

Verification IPs should be as highly reused as design IPs are; in order to facilitate the reuse of components, deliverables and procedures have to be set in place among different developments.

In the same way in which the design IP has a list of deliverables, the verification environment and IPs have to be subject to a similar list of requirements; the list is used to make sure that no integration problems are found later and, if any, the debug time is minimized.

Application Domains

Since its inception in 1999, NoBug has been involved in a large variety of verification projects, which span all types of tools, methodologies and designs.

A representation of the flows, methodologies and tools knowledge inside NoBug is given in the following charts.

ASIC Flow Skills, such as:

EDL Standards & Scripting
(2014)

EDA Tools & Methods

(2014)


(2014)

The designs submitted for verification to NoBug belong to application domains such as: network processors, storage processors, multimedia, controllers and peripherals, mobile applications, automotive, software validation etc.

The phases NoBug support is requested with partial or full responsibility span from block-level to post-silicon validation passing by chip, sub-system, system level verification.

A representation of the effort per architecture and phases of various application domains projects is given in the charts below.

NoBug Total Effort/Architecture

(2014)

NoBug Total Effort/Phase

(2014)

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